1. Field of the Invention
This invention relates to improvements in methods and apparatus for testing very large scale integrated memory circuits, and, more particularly, to improvements in methods and apparatus for testing such circuits using circuitry fabricated onto the integrated circuit chip itself.
2. Description of the Prior Art
In the design and fabrication of very large scale integrated (VLSI) memory circuits, recent emphasis has been in constructing larger and larger memory arrays onto constant or smaller sized semiconductor chips. However, as the number of memory elements included on a chip becomes larger and larger, the testing of the circuits becomes more and more difficult and requires more and more time. Thus, in the fabrication of VLSI memory arrays with a large number of memory elements, the time required for testing the arrays becomes a significant proportion of the total manufacturing process. Even after manufacture, in the field in use, often times testing a particular memory array is desired in fault checking, system diagnosis, and so forth, and when very large numbers of memory elements are involved, the testing task becomes especially significant, and sometimes extremely burdensome.
More particularly, it is very difficult to test individual memory elements of a VLSI circuit from outside the circuit, and, additionally, it is extremely time consuming to apply test patterns to the circuit from outside the chip, then read all of the memory cells of the chip and analyze the data obtained. In the past, for example, computer programs have been developed to apply particular testing algorithms to a particular memory chip or array to be tested. As each of the input signals is applied to the memory elements, they are directed to respective selected memory elements, and an output is developed which indicates whether a particular selected individual memory element has the desired contents in it. Doing this on an individual circuit-by-circuit basis (or element-by-element basis), becomes difficult when one considers the large size of memory elements contained on a single chip, for example, memory elements in excess of 256K. Thus, techniques have been developed in the past to streamline or make more efficient such testing techniques. An example of such technique outside of the LSI or integrated circuit arena, is in the provision of a parallel signature analyzer in which output signals from, for example, a memory array to be tested can be examined after a known sequence of signals have been applied and written into the memory array. The parallel signature analyzer reads the memory and develops an output which is examined and compared to an expected output signature. The signature developed by the parallel signature analyzer thus indicates that all of the memory elements are properly functioning if the known signature is developed.
In general, the memory tests commonly used involving parallel signature analyzers involve writing predetermined memory states into the memory, then reading the memory to determine whether what is read is the same as what was written. Because of the large quantity of data developed, however, it has been found that the data can be compressed by appropriate logic circuits into a so called "signature", which can be compared to a signature developed by a known, good memory circuit. Thus, in a parallel signature analyzer, the individual memory contents applied to the inputs of the parallel signature analyzer are combined through appropriate combinational logic which is known to the tester so that the desired signature can be developed.
An example of a parallel signature analyzer can be seen, for example, in co-pending U.S. patent application Ser. No. 551,667, filed Nov. 10, 1983, entitled "Universal Testing Circuit and Method", and assigned to the assignee hereof, said patent application being incorporated therein by reference as background. Such parallel signature analyzer operates in several modes relevant to the present invention. The first mode is a "scan" mode in which data is scanned into the parallel signature analyzer and made available at its output for application to a memory device under test. (As will become apparent, a "write" mode in which the contents scanned into the parallel signature analyzer are written into the memory is advanced hereinbelow, and is not a part of the art known herebefore.) A second mode is a "read" mode in which data appearing at the input to the parallel signature analyzer is received by the parallel signature analyzer and applied to its particular combinational logic, and additional subsequently applied input data is applied and combined with the earlier inputted data, and so forth, until a time after which all of the data has been applied and a particular output "signature" is generated for comparision with a known required signature.